By Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
Advanced try equipment for SRAMs: powerful ideas for Dynamic Fault Detection in Nanoscaled Technologies
Modern electronics relies on nanoscaled applied sciences that current new demanding situations by way of checking out and analysis. thoughts are rather liable to defects when you consider that they make the most the know-how limits to get the top density. This ebook is a useful advisor to the checking out and prognosis of the newest new release of SRAM, some of the most commonly used kind of stories. Classical tools for trying out reminiscence are designed to address the so-called "static faults", yet those try ideas usually are not adequate for faults which are rising within the newest Very Deep Sub-Micron (VDSM) applied sciences. those new faults, often called "dynamic faults", are usually not lined by means of classical algorithms and require the committed attempt and analysis suggestions offered during this book.
- First booklet to offer entire, state of the art insurance of dynamic fault checking out for SRAM memories;
- Presents content material utilizing a "bottom-up" strategy, from the research of explanations of malfunctions as much as the new release of clever attempt techniques;
- Includes case reviews protecting all reminiscence parts (core-cells, handle decoders, write drivers, feel amplifiers, etc.);
- Proposes an exhaustive research of resistive-open defects in every one reminiscence part and the ensuing dynamic fault modeling.
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Extra info for Advanced Test Methods for SRAMs: Effective Solutions for Dynamic Fault Detection in Nanoscaled Technologies
In memories, the devices that may switch are the core-cells, the output circuits, and the addressing circuits, especially those used for the column selection that commonly employ several levels of multiplexers. On the basis of these considerations, an algorithmic procedure that maximizes the detection of defects Df2 and Df3 can be formulated. As done for the detection of dRDFs, existing March test with the addressing order word line after word line can be used for the production of RESs in sequence.
Defect Df1: This defect produces a delay in the charging/discharging operation of node SB during the write operations. The defect essentially leads to a transition fault (TF). This fault is static and many common March tests are able to 24 Fig. 4 Resistive-open defects injected into the memory core-cell 2 Resistive-Open Defects in Core-Cells BL Df5 VDD Df4 BLB WLS Mtp2 Df2 SB Mtn2 Mtn3 Df3 S Df1 Mtn4 VDD Mtp1 Df6 Mtn1 – – – – detect it. ’ Defect Df2: This defect induces a delay in the output of INV1 especially during the discharge of node SB.
M is the number of read operations performed after the write operation (M ≥ 1). – FP4: <0w1 r1 M /0/0> A logic ‘0’ is initially stored in the cell. A w1 operation immediately followed by M r1 operations causes the swap of the core-cell content, and a logic ‘0’ is observed at the memory output. M is the number of read operations performed after the write operation (M ≥ 1). 2 RES: Read Equivalent Stress The dRDF can be the consequence of resistive-open defects in the core-cell of SRAMs. In particular, it has been empathized above that, in presence of resistiveopen defect Df4 depicted in Fig.
Advanced Test Methods for SRAMs: Effective Solutions for Dynamic Fault Detection in Nanoscaled Technologies by Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel